Автор работы: Пользователь скрыл имя, 01 Декабря 2012 в 20:48, курсовая работа
IP-ядро является блоком логической схемы, которое используется в изготовлении программируемой матрицы логических элементов или специальных интегральных схем. Таким образом, IP-ядро является универсальным элементом при построении интегральных схем. Идеально, IP ядро должно быть полностью переносным – то есть легко устанавливаемым в любую технику. Универсальные асинхронные приемопередатчики, центральные процессоры, регуляторы (контроллеры) Ethernet, и интерфейсы PCI – все примеры ядер IP.
Календарный план
Аннотация
Введение
Техническое задание
Разработка VHDL модели проектируемого устройства
• Граф переходов состояний микропроцессора
• Синтез устройства
• Структурная схема устройства
• Текст программы на языке VHDL
RB2(2) <= L4(2) OR L2(2);
RB2(3) <= L4(3) OR L2(3);
RB2(4) <= L4(4) OR L2(4);
RB2(5) <= L4(5) OR L2(5);
RB2(6) <= L4(6) OR L2(6);
RB2(7) <= L4(7) OR L2(7);
when "00001000" =>
RB3(0) <= L1(0) OR L3(0);
RB3(1) <= L1(1) OR L3(1);
RB3(2) <= L1(2) OR L3(2);
RB3(3) <= L1(3) OR L3(3);
RB3(4) <= L1(4) OR L3(4);
RB3(5) <= L1(5) OR L3(5);
RB3(6) <= L1(6) OR L3(6);
RB3(7) <= L1(7) OR L3(7);
when "00011000" =>
RB3(0) <= L2(0) OR L3(0);
RB3(1) <= L2(1) OR L3(1);
RB3(2) <= L2(2) OR L3(2);
RB3(3) <= L2(3) OR L3(3);
RB3(4) <= L2(4) OR L3(4);
RB3(5) <= L2(5) OR L3(5);
RB3(6) <= L2(6) OR L3(6);
RB3(7) <= L2(7) OR L3(7);
when "00101000" =>
RB3(0) <= L3(0) OR L3(0);
RB3(1) <= L3(1) OR L3(1);
RB3(2) <= L3(2) OR L3(2);
RB3(3) <= L3(3) OR L3(3);
RB3(4) <= L3(4) OR L3(4);
RB3(5) <= L3(5) OR L3(5);
RB3(6) <= L3(6) OR L3(6);
RB3(7) <= L3(7) OR L3(7);
when "00111000" =>
RB3(0) <= L4(0) OR L3(0);
RB3(1) <= L4(1) OR L3(1);
RB3(2) <= L4(2) OR L3(2);
RB3(3) <= L4(3) OR L3(3);
RB3(4) <= L4(4) OR L3(4);
RB3(5) <= L4(5) OR L3(5);
RB3(6) <= L4(6) OR L3(6);
RB3(7) <= L4(7) OR L3(7);
when "00001100" =>
RB4(0) <= L1(0) OR L4(0);
RB4(1) <= L1(1) OR L4(1);
RB4(2) <= L1(2) OR L4(2);
RB4(3) <= L1(3) OR L4(3);
RB4(4) <= L1(4) OR L4(4);
RB4(5) <= L1(5) OR L4(5);
RB4(6) <= L1(6) OR L4(6);
RB4(7) <= L1(7) OR L4(7);
when "00011100" =>
RB4(0) <= L2(0) OR L4(0);
RB4(1) <= L2(1) OR L4(1);
RB4(2) <= L2(2) OR L4(2);
RB4(3) <= L2(3) OR L4(3);
RB4(4) <= L2(4) OR L4(4);
RB4(5) <= L2(5) OR L4(5);
RB4(6) <= L2(6) OR L4(6);
RB4(7) <= L2(7) OR L4(7);
when "00101100" =>
RB4(0) <= L3(0) OR L4(0);
RB4(1) <= L3(1) OR L4(1);
RB4(2) <= L3(2) OR L4(2);
RB4(3) <= L3(3) OR L4(3);
RB4(4) <= L3(4) OR L4(4);
RB4(5) <= L3(5) OR L4(5);
RB4(6) <= L3(6) OR L4(6);
RB4(7) <= L3(7) OR L4(7);
when "00111100" =>
RB4(0) <= L4(0) OR L4(0);
RB4(1) <= L4(1) OR L4(1);
RB4(2) <= L4(2) OR L4(2);
RB4(3) <= L4(3) OR L4(3);
RB4(4) <= L4(4) OR L4(4);
RB4(5) <= L4(5) OR L4(5);
RB4(6) <= L4(6) OR L4(6);
RB4(7) <= L4(7) OR L4(7);
------------------------------
when "00000001" =>
RB1(0) <= L1(0) AND L1(0);
RB1(1) <= L1(1) AND L1(1);
RB1(2) <= L1(2) AND L1(2);
RB1(3) <= L1(3) AND L1(3);
RB1(4) <= L1(4) AND L1(4);
RB1(5) <= L1(5) AND L1(5);
RB1(6) <= L1(6) AND L1(6);
RB1(7) <= L1(7) AND L1(7);
when "00010001" =>
RB1(0) <= L2(0) AND L1(0);
RB1(1) <= L2(1) AND L1(1);
RB1(2) <= L2(2) AND L1(2);
RB1(3) <= L2(3) AND L1(3);
RB1(4) <= L2(4) AND L1(4);
RB1(5) <= L2(5) AND L1(5);
RB1(6) <= L2(6) AND L1(6);
RB1(7) <= L2(7) AND L1(7);
when "00100001" =>
RB1(0) <= L3(0) AND L1(0);
RB1(1) <= L3(1) AND L1(1);
RB1(2) <= L3(2) AND L1(2);
RB1(3) <= L3(3) AND L1(3);
RB1(4) <= L3(4) AND L1(4);
RB1(5) <= L3(5) AND L1(5);
RB1(6) <= L3(6) AND L1(6);
RB1(7) <= L3(7) AND L1(7);
when "00110001" =>
RB1(0) <= L4(0) AND L1(0);
RB1(1) <= L4(1) AND L1(1);
RB1(2) <= L4(2) AND L1(2);
RB1(3) <= L4(3) AND L1(3);
RB1(4) <= L4(4) AND L1(4);
RB1(5) <= L4(5) AND L1(5);
RB1(6) <= L4(6) AND L1(6);
RB1(7) <= L4(7) AND L1(7);
when "00000101" =>
RB2(0) <= L1(0) AND L2(0);
RB2(1) <= L1(1) AND L2(1);
RB2(2) <= L1(2) AND L2(2);
RB2(3) <= L1(3) AND L2(3);
RB2(4) <= L1(4) AND L2(4);
RB2(5) <= L1(5) AND L2(5);
RB2(6) <= L1(6) AND L2(6);
RB2(7) <= L1(7) AND L2(7);
when "00010101" =>
RB2(0) <= L2(0) AND L2(0);
RB2(1) <= L2(1) AND L2(1);
RB2(2) <= L2(2) AND L2(2);
RB2(3) <= L2(3) AND L2(3);
RB2(4) <= L2(4) AND L2(4);
RB2(5) <= L2(5) AND L2(5);
RB2(6) <= L2(6) AND L2(6);
RB2(7) <= L2(7) AND L2(7);
when "00100101" =>
RB2(0) <= L3(0) AND L2(0);
RB2(1) <= L3(1) AND L2(1);
RB2(2) <= L3(2) AND L2(2);
RB2(3) <= L3(3) AND L2(3);
RB2(4) <= L3(4) AND L2(4);
RB2(5) <= L3(5) AND L2(5);
RB2(6) <= L3(6) AND L2(6);
RB2(7) <= L3(7) AND L2(7);
when "00110101" =>
RB2(0) <= L4(0) AND L2(0);
RB2(1) <= L4(1) AND L2(1);
RB2(2) <= L4(2) AND L2(2);
RB2(3) <= L4(3) AND L2(3);
RB2(4) <= L4(4) AND L2(4);
RB2(5) <= L4(5) AND L2(5);
RB2(6) <= L4(6) AND L2(6);
RB2(7) <= L4(7) AND L2(7);
when "00001001" =>
RB3(0) <= L1(0) AND L3(0);
RB3(1) <= L1(1) AND L3(1);
RB3(2) <= L1(2) AND L3(2);
RB3(3) <= L1(3) AND L3(3);
RB3(4) <= L1(4) AND L3(4);
RB3(5) <= L1(5) AND L3(5);
RB3(6) <= L1(6) AND L3(6);
RB3(7) <= L1(7) AND L3(7);
when "00011001" =>
RB3(0) <= L2(0) AND L3(0);
RB3(1) <= L2(1) AND L3(1);
RB3(2) <= L2(2) AND L3(2);
RB3(3) <= L2(3) AND L3(3);
RB3(4) <= L2(4) AND L3(4);
RB3(5) <= L2(5) AND L3(5);
RB3(6) <= L2(6) AND L3(6);
RB3(7) <= L2(7) AND L3(7);
when "00101001" =>
RB3(0) <= L3(0) AND L3(0);
RB3(1) <= L3(1) AND L3(1);
RB3(2) <= L3(2) AND L3(2);
RB3(3) <= L3(3) AND L3(3);
RB3(4) <= L3(4) AND L3(4);
RB3(5) <= L3(5) AND L3(5);
RB3(6) <= L3(6) AND L3(6);
RB3(7) <= L3(7) AND L3(7);
when "00111001" =>
RB3(0) <= L4(0) AND L3(0);
RB3(1) <= L4(1) AND L3(1);
RB3(2) <= L4(2) AND L3(2);
RB3(3) <= L4(3) AND L3(3);
RB3(4) <= L4(4) AND L3(4);
RB3(5) <= L4(5) AND L3(5);
RB3(6) <= L4(6) AND L3(6);
RB3(7) <= L4(7) AND L3(7);
when "00001101" =>
RB4(0) <= L1(0) AND L4(0);
RB4(1) <= L1(1) AND L4(1);
RB4(2) <= L1(2) AND L4(2);
RB4(3) <= L1(3) AND L4(3);
RB4(4) <= L1(4) AND L4(4);
RB4(5) <= L1(5) AND L4(5);
RB4(6) <= L1(6) AND L4(6);
RB4(7) <= L1(7) AND L4(7);
when "00011101" =>
RB4(0) <= L2(0) AND L4(0);
RB4(1) <= L2(1) AND L4(1);
RB4(2) <= L2(2) AND L4(2);
RB4(3) <= L2(3) AND L4(3);
RB4(4) <= L2(4) AND L4(4);
RB4(5) <= L2(5) AND L4(5);
RB4(6) <= L2(6) AND L4(6);
RB4(7) <= L2(7) AND L4(7);
when "00101101" =>
RB4(0) <= L3(0) AND L4(0);
RB4(1) <= L3(1) AND L4(1);
RB4(2) <= L3(2) AND L4(2);
RB4(3) <= L3(3) AND L4(3);
RB4(4) <= L3(4) AND L4(4);
RB4(5) <= L3(5) AND L4(5);
RB4(6) <= L3(6) AND L4(6);
RB4(7) <= L3(7) AND L4(7);
when "00111101" =>
RB4(0) <= L4(0) AND L4(0);
RB4(1) <= L4(1) AND L4(1);
RB4(2) <= L4(2) AND L4(2);
RB4(3) <= L4(3) AND L4(3);
RB4(4) <= L4(4) AND L4(4);
RB4(5) <= L4(5) AND L4(5);
RB4(6) <= L4(6) AND L4(6);
RB4(7) <= L4(7) AND L4(7);
------------------------------
when "00000011" =>
RB1(0) <= L1(0) XOR L1(0);
RB1(1) <= L1(1) XOR L1(1);
RB1(2) <= L1(2) XOR L1(2);
RB1(3) <= L1(3) XOR L1(3);
RB1(4) <= L1(4) XOR L1(4);
RB1(5) <= L1(5) XOR L1(5);
RB1(6) <= L1(6) XOR L1(6);
RB1(7) <= L1(7) XOR L1(7);
when "00010011" =>
RB1(0) <= L2(0) XOR L1(0);
RB1(1) <= L2(1) XOR L1(1);
RB1(2) <= L2(2) XOR L1(2);
RB1(3) <= L2(3) XOR L1(3);
RB1(4) <= L2(4) XOR L1(4);
RB1(5) <= L2(5) XOR L1(5);
RB1(6) <= L2(6) XOR L1(6);
RB1(7) <= L2(7) XOR L1(7);
when "00100011" =>
RB1(0) <= L3(0) XOR L1(0);
RB1(1) <= L3(1) XOR L1(1);
RB1(2) <= L3(2) XOR L1(2);
RB1(3) <= L3(3) XOR L1(3);
RB1(4) <= L3(4) XOR L1(4);
RB1(5) <= L3(5) XOR L1(5);
RB1(6) <= L3(6) XOR L1(6);
RB1(7) <= L3(7) XOR L1(7);
when "00110011" =>
RB1(0) <= L4(0) XOR L1(0);
RB1(1) <= L4(1) XOR L1(1);
RB1(2) <= L4(2) XOR L1(2);
RB1(3) <= L4(3) XOR L1(3);
RB1(4) <= L4(4) XOR L1(4);
RB1(5) <= L4(5) XOR L1(5);
RB1(6) <= L4(6) XOR L1(6);
RB1(7) <= L4(7) XOR L1(7);
when "00000111" =>
RB2(0) <= L1(0) XOR L2(0);
RB2(1) <= L1(1) XOR L2(1);
RB2(2) <= L1(2) XOR L2(2);
RB2(3) <= L1(3) XOR L2(3);
RB2(4) <= L1(4) XOR L2(4);
RB2(5) <= L1(5) XOR L2(5);
RB2(6) <= L1(6) XOR L2(6);
RB2(7) <= L1(7) XOR L2(7);
when "00010111" =>
RB2(0) <= L2(0) XOR L2(0);
RB2(1) <= L2(1) XOR L2(1);
RB2(2) <= L2(2) XOR L2(2);
RB2(3) <= L2(3) XOR L2(3);
RB2(4) <= L2(4) XOR L2(4);
RB2(5) <= L2(5) XOR L2(5);
RB2(6) <= L2(6) XOR L2(6);
RB2(7) <= L2(7) XOR L2(7);
when "00100111" =>
RB2(0) <= L3(0) XOR L2(0);
RB2(1) <= L3(1) XOR L2(1);
RB2(2) <= L3(2) XOR L2(2);
RB2(3) <= L3(3) XOR L2(3);
RB2(4) <= L3(4) XOR L2(4);
RB2(5) <= L3(5) XOR L2(5);
RB2(6) <= L3(6) XOR L2(6);
RB2(7) <= L3(7) XOR L2(7);
when "00110111" =>
RB2(0) <= L4(0) XOR L2(0);
RB2(1) <= L4(1) XOR L2(1);
RB2(2) <= L4(2) XOR L2(2);
RB2(3) <= L4(3) XOR L2(3);
RB2(4) <= L4(4) XOR L2(4);
RB2(5) <= L4(5) XOR L2(5);
RB2(6) <= L4(6) XOR L2(6);
RB2(7) <= L4(7) XOR L2(7);
when "00001011" =>
RB3(0) <= L1(0) XOR L3(0);
RB3(1) <= L1(1) XOR L3(1);
RB3(2) <= L1(2) XOR L3(2);
RB3(3) <= L1(3) XOR L3(3);
RB3(4) <= L1(4) XOR L3(4);
RB3(5) <= L1(5) XOR L3(5);
RB3(6) <= L1(6) XOR L3(6);
RB3(7) <= L1(7) XOR L3(7);
when "00011011" =>
RB3(0) <= L2(0) XOR L3(0);
RB3(1) <= L2(1) XOR L3(1);
RB3(2) <= L2(2) XOR L3(2);
RB3(3) <= L2(3) XOR L3(3);
RB3(4) <= L2(4) XOR L3(4);
RB3(5) <= L2(5) XOR L3(5);
RB3(6) <= L2(6) XOR L3(6);
RB3(7) <= L2(7) XOR L3(7);
when "00101011" =>
RB3(0) <= L3(0) XOR L3(0);
RB3(1) <= L3(1) XOR L3(1);
RB3(2) <= L3(2) XOR L3(2);
RB3(3) <= L3(3) XOR L3(3);
RB3(4) <= L3(4) XOR L3(4);
RB3(5) <= L3(5) XOR L3(5);
RB3(6) <= L3(6) XOR L3(6);
RB3(7) <= L3(7) XOR L3(7);
Информация о работе Разработка IP - ядра коммутационного микропроцессора