Автор работы: Пользователь скрыл имя, 01 Декабря 2012 в 20:48, курсовая работа
IP-ядро является блоком логической схемы, которое используется в изготовлении программируемой матрицы логических элементов или специальных интегральных схем. Таким образом, IP-ядро является универсальным элементом при построении интегральных схем. Идеально, IP ядро должно быть полностью переносным – то есть легко устанавливаемым в любую технику. Универсальные асинхронные приемопередатчики, центральные процессоры, регуляторы (контроллеры) Ethernet, и интерфейсы PCI – все примеры ядер IP.
Календарный план
Аннотация
Введение
Техническое задание
Разработка VHDL модели проектируемого устройства
• Граф переходов состояний микропроцессора
• Синтез устройства
• Структурная схема устройства
• Текст программы на языке VHDL
when "00111011" =>
RB3(0) <= L4(0) XOR L3(0);
RB3(1) <= L4(1) XOR L3(1);
RB3(2) <= L4(2) XOR L3(2);
RB3(3) <= L4(3) XOR L3(3);
RB3(4) <= L4(4) XOR L3(4);
RB3(5) <= L4(5) XOR L3(5);
RB3(6) <= L4(6) XOR L3(6);
RB3(7) <= L4(7) XOR L3(7);
when "00001111" =>
RB4(0) <= L1(0) XOR L4(0);
RB4(1) <= L1(1) XOR L4(1);
RB4(2) <= L1(2) XOR L4(2);
RB4(3) <= L1(3) XOR L4(3);
RB4(4) <= L1(4) XOR L4(4);
RB4(5) <= L1(5) XOR L4(5);
RB4(6) <= L1(6) XOR L4(6);
RB4(7) <= L1(7) XOR L4(7);
when "00011111" =>
RB4(0) <= L2(0) XOR L4(0);
RB4(1) <= L2(1) XOR L4(1);
RB4(2) <= L2(2) XOR L4(2);
RB4(3) <= L2(3) XOR L4(3);
RB4(4) <= L2(4) XOR L4(4);
RB4(5) <= L2(5) XOR L4(5);
RB4(6) <= L2(6) XOR L4(6);
RB4(7) <= L2(7) XOR L4(7);
when "00101111" =>
RB4(0) <= L3(0) XOR L4(0);
RB4(1) <= L3(1) XOR L4(1);
RB4(2) <= L3(2) XOR L4(2);
RB4(3) <= L3(3) XOR L4(3);
RB4(4) <= L3(4) XOR L4(4);
RB4(5) <= L3(5) XOR L4(5);
RB4(6) <= L3(6) XOR L4(6);
RB4(7) <= L3(7) XOR L4(7);
when "00111111" =>
RB4(0) <= L4(0) XOR L4(0);
RB4(1) <= L4(1) XOR L4(1);
RB4(2) <= L4(2) XOR L4(2);
RB4(3) <= L4(3) XOR L4(3);
RB4(4) <= L4(4) XOR L4(4);
RB4(5) <= L4(5) XOR L4(5);
RB4(6) <= L4(6) XOR L4(6);
RB4(7) <= L4(7) XOR L4(7);
------------------------------
when "00000000" => RB1(0 to 7) <= L1(0 to 7);
when "00010000" => RB1(0 to 7) <= L2(0 to 7);
when "00100000" => RB1(0 to 7) <= L3(0 to 7);
when "00110000" => RB1(0 to 7) <= L4(0 to 7);
when "00000100" => RB2(0 to 7) <= L1(0 to 7);
when "00010100" => RB2(0 to 7) <= L2(0 to 7);
when "00100100" => RB2(0 to 7) <= L3(0 to 7);
when "00110100" => RB2(0 to 7) <= L4(0 to 7);
when "00001000" => RB3(0 to 7) <= L1(0 to 7);
when "00011000" => RB3(0 to 7) <= L2(0 to 7);
when "00101000" => RB3(0 to 7) <= L3(0 to 7);
when "00111000" => RB3(0 to 7) <= L4(0 to 7);
when "00001100" => RB4(0 to 7) <= L1(0 to 7);
when "00011100" => RB4(0 to 7) <= L2(0 to 7);
when "00101100" => RB4(0 to 7) <= L3(0 to 7);
when "00111100" => RB4(0 to 7) <= L4(0 to 7);
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---------------microcomand 3 - at mng_device--------------------
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--#(a,b,c,d) = (a*b*c)+(a*b*d)+(a*c*d)+(b*c*
--when "1001JJ" => RBj=L1#L2#L3#L4;
when "10010000" =>
RB1(0)<= (L1(0) and L2(0) and L3(0))+(L1(0) and L2(0) and L4(0))+(L1(0) and L3(0) and L4(0))+(L2(0) and L3(0) and L4(0));
RB1(1)<= (L1(1) and L2(1) and L3(1))+(L1(1) and L2(1) and L4(1))+(L1(1) and L3(1) and L4(1))+(L2(1) and L3(1) and L4(1));
RB1(2)<= (L1(2) and L2(2) and L3(2))+(L1(2) and L2(2) and L4(2))+(L1(2) and L3(2) and L4(2))+(L2(2) and L3(2) and L4(2));
RB1(3)<= (L1(3) and L2(3) and L3(3))+(L1(3) and L2(3) and L4(3))+(L1(3) and L3(3) and L4(3))+(L2(3) and L3(3) and L4(3));
RB1(4)<= (L1(4) and L2(4) and L3(4))+(L1(4) and L2(4) and L4(4))+(L1(4) and L3(4) and L4(4))+(L2(4) and L3(4) and L4(4));
RB1(5)<= (L1(5) and L2(5) and L3(5))+(L1(5) and L2(5) and L4(5))+(L1(5) and L3(5) and L4(5))+(L2(5) and L3(5) and L4(5));
RB1(6)<= (L1(6) and L2(6) and L3(6))+(L1(6) and L2(6) and L4(6))+(L1(6) and L3(6) and L4(6))+(L2(6) and L3(6) and L4(6));
RB1(7)<= (L1(7) and L2(7) and L3(7))+(L1(7) and L2(7) and L4(7))+(L1(7) and L3(7) and L4(7))+(L2(7) and L3(7) and L4(7));
when "10010100" =>
RB2(0)<= (L1(0) and L2(0) and L3(0))+(L1(0) and L2(0) and L4(0))+(L1(0) and L3(0) and L4(0))+(L2(0) and L3(0) and L4(0));
RB2(1)<= (L1(1) and L2(1) and L3(1))+(L1(1) and L2(1) and L4(1))+(L1(1) and L3(1) and L4(1))+(L2(1) and L3(1) and L4(1));
RB2(2)<= (L1(2) and L2(2) and L3(2))+(L1(2) and L2(2) and L4(2))+(L1(2) and L3(2) and L4(2))+(L2(2) and L3(2) and L4(2));
RB2(3)<= (L1(3) and L2(3) and L3(3))+(L1(3) and L2(3) and L4(3))+(L1(3) and L3(3) and L4(3))+(L2(3) and L3(3) and L4(3));
RB2(4)<= (L1(4) and L2(4) and L3(4))+(L1(4) and L2(4) and L4(4))+(L1(4) and L3(4) and L4(4))+(L2(4) and L3(4) and L4(4));
RB2(5)<= (L1(5) and L2(5) and L3(5))+(L1(5) and L2(5) and L4(5))+(L1(5) and L3(5) and L4(5))+(L2(5) and L3(5) and L4(5));
RB2(6)<= (L1(6) and L2(6) and L3(6))+(L1(6) and L2(6) and L4(6))+(L1(6) and L3(6) and L4(6))+(L2(6) and L3(6) and L4(6));
RB2(7)<= (L1(7) and L2(7) and L3(7))+(L1(7) and L2(7) and L4(7))+(L1(7) and L3(7) and L4(7))+(L2(7) and L3(7) and L4(7));
when "10011000" =>
RB3(0)<= (L1(0) and L2(0) and L3(0))+(L1(0) and L2(0) and L4(0))+(L1(0) and L3(0) and L4(0))+(L2(0) and L3(0) and L4(0));
RB3(1)<= (L1(1) and L2(1) and L3(1))+(L1(1) and L2(1) and L4(1))+(L1(1) and L3(1) and L4(1))+(L2(1) and L3(1) and L4(1));
RB3(2)<= (L1(2) and L2(2) and L3(2))+(L1(2) and L2(2) and L4(2))+(L1(2) and L3(2) and L4(2))+(L2(2) and L3(2) and L4(2));
RB3(3)<= (L1(3) and L2(3) and L3(3))+(L1(3) and L2(3) and L4(3))+(L1(3) and L3(3) and L4(3))+(L2(3) and L3(3) and L4(3));
RB3(4)<= (L1(4) and L2(4) and L3(4))+(L1(4) and L2(4) and L4(4))+(L1(4) and L3(4) and L4(4))+(L2(4) and L3(4) and L4(4));
RB3(5)<= (L1(5) and L2(5) and L3(5))+(L1(5) and L2(5) and L4(5))+(L1(5) and L3(5) and L4(5))+(L2(5) and L3(5) and L4(5));
RB3(6)<= (L1(6) and L2(6) and L3(6))+(L1(6) and L2(6) and L4(6))+(L1(6) and L3(6) and L4(6))+(L2(6) and L3(6) and L4(6));
RB3(7)<= (L1(7) and L2(7) and L3(7))+(L1(7) and L2(7) and L4(7))+(L1(7) and L3(7) and L4(7))+(L2(7) and L3(7) and L4(7));
when "10011100" =>
RB4(0)<= (L1(0) and L2(0) and L3(0))+(L1(0) and L2(0) and L4(0))+(L1(0) and L3(0) and L4(0))+(L2(0) and L3(0) and L4(0));
RB4(1)<= (L1(1) and L2(1) and L3(1))+(L1(1) and L2(1) and L4(1))+(L1(1) and L3(1) and L4(1))+(L2(1) and L3(1) and L4(1));
RB4(2)<= (L1(2) and L2(2) and L3(2))+(L1(2) and L2(2) and L4(2))+(L1(2) and L3(2) and L4(2))+(L2(2) and L3(2) and L4(2));
RB4(3)<= (L1(3) and L2(3) and L3(3))+(L1(3) and L2(3) and L4(3))+(L1(3) and L3(3) and L4(3))+(L2(3) and L3(3) and L4(3));
RB4(4)<= (L1(4) and L2(4) and L3(4))+(L1(4) and L2(4) and L4(4))+(L1(4) and L3(4) and L4(4))+(L2(4) and L3(4) and L4(4));
RB4(5)<= (L1(5) and L2(5) and L3(5))+(L1(5) and L2(5) and L4(5))+(L1(5) and L3(5) and L4(5))+(L2(5) and L3(5) and L4(5));
RB4(6)<= (L1(6) and L2(6) and L3(6))+(L1(6) and L2(6) and L4(6))+(L1(6) and L3(6) and L4(6))+(L2(6) and L3(6) and L4(6));
RB4(7)<= (L1(7) and L2(7) and L3(7))+(L1(7) and L2(7) and L4(7))+(L1(7) and L3(7) and L4(7))+(L2(7) and L3(7) and L4(7));
----------
when "10010001" =>
RB1(0)<= (L1(0) and L2(0) and L3(0))+(L1(0) and L2(0) and L4(0))+(L1(0) and L3(0) and L4(0))+(L2(0) and L3(0) and L4(0));
RB1(1)<= (L1(1) and L2(1) and L3(1))+(L1(1) and L2(1) and L4(1))+(L1(1) and L3(1) and L4(1))+(L2(1) and L3(1) and L4(1));
RB1(2)<= (L1(2) and L2(2) and L3(2))+(L1(2) and L2(2) and L4(2))+(L1(2) and L3(2) and L4(2))+(L2(2) and L3(2) and L4(2));
RB1(3)<= (L1(3) and L2(3) and L3(3))+(L1(3) and L2(3) and L4(3))+(L1(3) and L3(3) and L4(3))+(L2(3) and L3(3) and L4(3));
RB1(4)<= (L1(4) and L2(4) and L3(4))+(L1(4) and L2(4) and L4(4))+(L1(4) and L3(4) and L4(4))+(L2(4) and L3(4) and L4(4));
RB1(5)<= (L1(5) and L2(5) and L3(5))+(L1(5) and L2(5) and L4(5))+(L1(5) and L3(5) and L4(5))+(L2(5) and L3(5) and L4(5));
RB1(6)<= (L1(6) and L2(6) and L3(6))+(L1(6) and L2(6) and L4(6))+(L1(6) and L3(6) and L4(6))+(L2(6) and L3(6) and L4(6));
RB1(7)<= (L1(7) and L2(7) and L3(7))+(L1(7) and L2(7) and L4(7))+(L1(7) and L3(7) and L4(7))+(L2(7) and L3(7) and L4(7));
when "10010101" =>
RB2(0)<= (L1(0) and L2(0) and L3(0))+(L1(0) and L2(0) and L4(0))+(L1(0) and L3(0) and L4(0))+(L2(0) and L3(0) and L4(0));
RB2(1)<= (L1(1) and L2(1) and L3(1))+(L1(1) and L2(1) and L4(1))+(L1(1) and L3(1) and L4(1))+(L2(1) and L3(1) and L4(1));
RB2(2)<= (L1(2) and L2(2) and L3(2))+(L1(2) and L2(2) and L4(2))+(L1(2) and L3(2) and L4(2))+(L2(2) and L3(2) and L4(2));
RB2(3)<= (L1(3) and L2(3) and L3(3))+(L1(3) and L2(3) and L4(3))+(L1(3) and L3(3) and L4(3))+(L2(3) and L3(3) and L4(3));
RB2(4)<= (L1(4) and L2(4) and L3(4))+(L1(4) and L2(4) and L4(4))+(L1(4) and L3(4) and L4(4))+(L2(4) and L3(4) and L4(4));
RB2(5)<= (L1(5) and L2(5) and L3(5))+(L1(5) and L2(5) and L4(5))+(L1(5) and L3(5) and L4(5))+(L2(5) and L3(5) and L4(5));
RB2(6)<= (L1(6) and L2(6) and L3(6))+(L1(6) and L2(6) and L4(6))+(L1(6) and L3(6) and L4(6))+(L2(6) and L3(6) and L4(6));
RB2(7)<= (L1(7) and L2(7) and L3(7))+(L1(7) and L2(7) and L4(7))+(L1(7) and L3(7) and L4(7))+(L2(7) and L3(7) and L4(7));
when "10011001" =>
RB3(0)<= (L1(0) and L2(0) and L3(0))+(L1(0) and L2(0) and L4(0))+(L1(0) and L3(0) and L4(0))+(L2(0) and L3(0) and L4(0));
RB3(1)<= (L1(1) and L2(1) and L3(1))+(L1(1) and L2(1) and L4(1))+(L1(1) and L3(1) and L4(1))+(L2(1) and L3(1) and L4(1));
RB3(2)<= (L1(2) and L2(2) and L3(2))+(L1(2) and L2(2) and L4(2))+(L1(2) and L3(2) and L4(2))+(L2(2) and L3(2) and L4(2));
RB3(3)<= (L1(3) and L2(3) and L3(3))+(L1(3) and L2(3) and L4(3))+(L1(3) and L3(3) and L4(3))+(L2(3) and L3(3) and L4(3));
RB3(4)<= (L1(4) and L2(4) and L3(4))+(L1(4) and L2(4) and L4(4))+(L1(4) and L3(4) and L4(4))+(L2(4) and L3(4) and L4(4));
RB3(5)<= (L1(5) and L2(5) and L3(5))+(L1(5) and L2(5) and L4(5))+(L1(5) and L3(5) and L4(5))+(L2(5) and L3(5) and L4(5));
RB3(6)<= (L1(6) and L2(6) and L3(6))+(L1(6) and L2(6) and L4(6))+(L1(6) and L3(6) and L4(6))+(L2(6) and L3(6) and L4(6));
RB3(7)<= (L1(7) and L2(7) and L3(7))+(L1(7) and L2(7) and L4(7))+(L1(7) and L3(7) and L4(7))+(L2(7) and L3(7) and L4(7));
when "10011101" =>
RB4(0)<= (L1(0) and L2(0) and L3(0))+(L1(0) and L2(0) and L4(0))+(L1(0) and L3(0) and L4(0))+(L2(0) and L3(0) and L4(0));
RB4(1)<= (L1(1) and L2(1) and L3(1))+(L1(1) and L2(1) and L4(1))+(L1(1) and L3(1) and L4(1))+(L2(1) and L3(1) and L4(1));
RB4(2)<= (L1(2) and L2(2) and L3(2))+(L1(2) and L2(2) and L4(2))+(L1(2) and L3(2) and L4(2))+(L2(2) and L3(2) and L4(2));
RB4(3)<= (L1(3) and L2(3) and L3(3))+(L1(3) and L2(3) and L4(3))+(L1(3) and L3(3) and L4(3))+(L2(3) and L3(3) and L4(3));
RB4(4)<= (L1(4) and L2(4) and L3(4))+(L1(4) and L2(4) and L4(4))+(L1(4) and L3(4) and L4(4))+(L2(4) and L3(4) and L4(4));
RB4(5)<= (L1(5) and L2(5) and L3(5))+(L1(5) and L2(5) and L4(5))+(L1(5) and L3(5) and L4(5))+(L2(5) and L3(5) and L4(5));
RB4(6)<= (L1(6) and L2(6) and L3(6))+(L1(6) and L2(6) and L4(6))+(L1(6) and L3(6) and L4(6))+(L2(6) and L3(6) and L4(6));
RB4(7)<= (L1(7) and L2(7) and L3(7))+(L1(7) and L2(7) and L4(7))+(L1(7) and L3(7) and L4(7))+(L2(7) and L3(7) and L4(7));
--------
----------
when "10010010" =>
RB1(0)<= (L1(0) and L2(0) and L3(0))+(L1(0) and L2(0) and L4(0))+(L1(0) and L3(0) and L4(0))+(L2(0) and L3(0) and L4(0));
RB1(1)<= (L1(1) and L2(1) and L3(1))+(L1(1) and L2(1) and L4(1))+(L1(1) and L3(1) and L4(1))+(L2(1) and L3(1) and L4(1));
RB1(2)<= (L1(2) and L2(2) and L3(2))+(L1(2) and L2(2) and L4(2))+(L1(2) and L3(2) and L4(2))+(L2(2) and L3(2) and L4(2));
RB1(3)<= (L1(3) and L2(3) and L3(3))+(L1(3) and L2(3) and L4(3))+(L1(3) and L3(3) and L4(3))+(L2(3) and L3(3) and L4(3));
RB1(4)<= (L1(4) and L2(4) and L3(4))+(L1(4) and L2(4) and L4(4))+(L1(4) and L3(4) and L4(4))+(L2(4) and L3(4) and L4(4));
RB1(5)<= (L1(5) and L2(5) and L3(5))+(L1(5) and L2(5) and L4(5))+(L1(5) and L3(5) and L4(5))+(L2(5) and L3(5) and L4(5));
RB1(6)<= (L1(6) and L2(6) and L3(6))+(L1(6) and L2(6) and L4(6))+(L1(6) and L3(6) and L4(6))+(L2(6) and L3(6) and L4(6));
RB1(7)<= (L1(7) and L2(7) and L3(7))+(L1(7) and L2(7) and L4(7))+(L1(7) and L3(7) and L4(7))+(L2(7) and L3(7) and L4(7));
when "10010110" =>
RB2(0)<= (L1(0) and L2(0) and L3(0))+(L1(0) and L2(0) and L4(0))+(L1(0) and L3(0) and L4(0))+(L2(0) and L3(0) and L4(0));
RB2(1)<= (L1(1) and L2(1) and L3(1))+(L1(1) and L2(1) and L4(1))+(L1(1) and L3(1) and L4(1))+(L2(1) and L3(1) and L4(1));
RB2(2)<= (L1(2) and L2(2) and L3(2))+(L1(2) and L2(2) and L4(2))+(L1(2) and L3(2) and L4(2))+(L2(2) and L3(2) and L4(2));
RB2(3)<= (L1(3) and L2(3) and L3(3))+(L1(3) and L2(3) and L4(3))+(L1(3) and L3(3) and L4(3))+(L2(3) and L3(3) and L4(3));
RB2(4)<= (L1(4) and L2(4) and L3(4))+(L1(4) and L2(4) and L4(4))+(L1(4) and L3(4) and L4(4))+(L2(4) and L3(4) and L4(4));
RB2(5)<= (L1(5) and L2(5) and L3(5))+(L1(5) and L2(5) and L4(5))+(L1(5) and L3(5) and L4(5))+(L2(5) and L3(5) and L4(5));
RB2(6)<= (L1(6) and L2(6) and L3(6))+(L1(6) and L2(6) and L4(6))+(L1(6) and L3(6) and L4(6))+(L2(6) and L3(6) and L4(6));
RB2(7)<= (L1(7) and L2(7) and L3(7))+(L1(7) and L2(7) and L4(7))+(L1(7) and L3(7) and L4(7))+(L2(7) and L3(7) and L4(7));
when "10011010" =>
RB3(0)<= (L1(0) and L2(0) and L3(0))+(L1(0) and L2(0) and L4(0))+(L1(0) and L3(0) and L4(0))+(L2(0) and L3(0) and L4(0));
RB3(1)<= (L1(1) and L2(1) and L3(1))+(L1(1) and L2(1) and L4(1))+(L1(1) and L3(1) and L4(1))+(L2(1) and L3(1) and L4(1));
RB3(2)<= (L1(2) and L2(2) and L3(2))+(L1(2) and L2(2) and L4(2))+(L1(2) and L3(2) and L4(2))+(L2(2) and L3(2) and L4(2));
RB3(3)<= (L1(3) and L2(3) and L3(3))+(L1(3) and L2(3) and L4(3))+(L1(3) and L3(3) and L4(3))+(L2(3) and L3(3) and L4(3));
RB3(4)<= (L1(4) and L2(4) and L3(4))+(L1(4) and L2(4) and L4(4))+(L1(4) and L3(4) and L4(4))+(L2(4) and L3(4) and L4(4));
RB3(5)<= (L1(5) and L2(5) and L3(5))+(L1(5) and L2(5) and L4(5))+(L1(5) and L3(5) and L4(5))+(L2(5) and L3(5) and L4(5));
RB3(6)<= (L1(6) and L2(6) and L3(6))+(L1(6) and L2(6) and L4(6))+(L1(6) and L3(6) and L4(6))+(L2(6) and L3(6) and L4(6));
RB3(7)<= (L1(7) and L2(7) and L3(7))+(L1(7) and L2(7) and L4(7))+(L1(7) and L3(7) and L4(7))+(L2(7) and L3(7) and L4(7));
when "10011110" =>
RB4(0)<= (L1(0) and L2(0) and L3(0))+(L1(0) and L2(0) and L4(0))+(L1(0) and L3(0) and L4(0))+(L2(0) and L3(0) and L4(0));
RB4(1)<= (L1(1) and L2(1) and L3(1))+(L1(1) and L2(1) and L4(1))+(L1(1) and L3(1) and L4(1))+(L2(1) and L3(1) and L4(1));
RB4(2)<= (L1(2) and L2(2) and L3(2))+(L1(2) and L2(2) and L4(2))+(L1(2) and L3(2) and L4(2))+(L2(2) and L3(2) and L4(2));
RB4(3)<= (L1(3) and L2(3) and L3(3))+(L1(3) and L2(3) and L4(3))+(L1(3) and L3(3) and L4(3))+(L2(3) and L3(3) and L4(3));
RB4(4)<= (L1(4) and L2(4) and L3(4))+(L1(4) and L2(4) and L4(4))+(L1(4) and L3(4) and L4(4))+(L2(4) and L3(4) and L4(4));
RB4(5)<= (L1(5) and L2(5) and L3(5))+(L1(5) and L2(5) and L4(5))+(L1(5) and L3(5) and L4(5))+(L2(5) and L3(5) and L4(5));
RB4(6)<= (L1(6) and L2(6) and L3(6))+(L1(6) and L2(6) and L4(6))+(L1(6) and L3(6) and L4(6))+(L2(6) and L3(6) and L4(6));
RB4(7)<= (L1(7) and L2(7) and L3(7))+(L1(7) and L2(7) and L4(7))+(L1(7) and L3(7) and L4(7))+(L2(7) and L3(7) and L4(7));
-----------
when "10010011" =>
RB1(0)<= (L1(0) and L2(0) and L3(0))+(L1(0) and L2(0) and L4(0))+(L1(0) and L3(0) and L4(0))+(L2(0) and L3(0) and L4(0));
RB1(1)<= (L1(1) and L2(1) and L3(1))+(L1(1) and L2(1) and L4(1))+(L1(1) and L3(1) and L4(1))+(L2(1) and L3(1) and L4(1));
RB1(2)<= (L1(2) and L2(2) and L3(2))+(L1(2) and L2(2) and L4(2))+(L1(2) and L3(2) and L4(2))+(L2(2) and L3(2) and L4(2));
RB1(3)<= (L1(3) and L2(3) and L3(3))+(L1(3) and L2(3) and L4(3))+(L1(3) and L3(3) and L4(3))+(L2(3) and L3(3) and L4(3));
RB1(4)<= (L1(4) and L2(4) and L3(4))+(L1(4) and L2(4) and L4(4))+(L1(4) and L3(4) and L4(4))+(L2(4) and L3(4) and L4(4));
RB1(5)<= (L1(5) and L2(5) and L3(5))+(L1(5) and L2(5) and L4(5))+(L1(5) and L3(5) and L4(5))+(L2(5) and L3(5) and L4(5));
RB1(6)<= (L1(6) and L2(6) and L3(6))+(L1(6) and L2(6) and L4(6))+(L1(6) and L3(6) and L4(6))+(L2(6) and L3(6) and L4(6));
RB1(7)<= (L1(7) and L2(7) and L3(7))+(L1(7) and L2(7) and L4(7))+(L1(7) and L3(7) and L4(7))+(L2(7) and L3(7) and L4(7));
when "10010111" =>
RB2(0)<= (L1(0) and L2(0) and L3(0))+(L1(0) and L2(0) and L4(0))+(L1(0) and L3(0) and L4(0))+(L2(0) and L3(0) and L4(0));
RB2(1)<= (L1(1) and L2(1) and L3(1))+(L1(1) and L2(1) and L4(1))+(L1(1) and L3(1) and L4(1))+(L2(1) and L3(1) and L4(1));
RB2(2)<= (L1(2) and L2(2) and L3(2))+(L1(2) and L2(2) and L4(2))+(L1(2) and L3(2) and L4(2))+(L2(2) and L3(2) and L4(2));
RB2(3)<= (L1(3) and L2(3) and L3(3))+(L1(3) and L2(3) and L4(3))+(L1(3) and L3(3) and L4(3))+(L2(3) and L3(3) and L4(3));
RB2(4)<= (L1(4) and L2(4) and L3(4))+(L1(4) and L2(4) and L4(4))+(L1(4) and L3(4) and L4(4))+(L2(4) and L3(4) and L4(4));
RB2(5)<= (L1(5) and L2(5) and L3(5))+(L1(5) and L2(5) and L4(5))+(L1(5) and L3(5) and L4(5))+(L2(5) and L3(5) and L4(5));
RB2(6)<= (L1(6) and L2(6) and L3(6))+(L1(6) and L2(6) and L4(6))+(L1(6) and L3(6) and L4(6))+(L2(6) and L3(6) and L4(6));
RB2(7)<= (L1(7) and L2(7) and L3(7))+(L1(7) and L2(7) and L4(7))+(L1(7) and L3(7) and L4(7))+(L2(7) and L3(7) and L4(7));
when "10011011" =>
RB3(0)<= (L1(0) and L2(0) and L3(0))+(L1(0) and L2(0) and L4(0))+(L1(0) and L3(0) and L4(0))+(L2(0) and L3(0) and L4(0));
RB3(1)<= (L1(1) and L2(1) and L3(1))+(L1(1) and L2(1) and L4(1))+(L1(1) and L3(1) and L4(1))+(L2(1) and L3(1) and L4(1));
RB3(2)<= (L1(2) and L2(2) and L3(2))+(L1(2) and L2(2) and L4(2))+(L1(2) and L3(2) and L4(2))+(L2(2) and L3(2) and L4(2));
RB3(3)<= (L1(3) and L2(3) and L3(3))+(L1(3) and L2(3) and L4(3))+(L1(3) and L3(3) and L4(3))+(L2(3) and L3(3) and L4(3));
RB3(4)<= (L1(4) and L2(4) and L3(4))+(L1(4) and L2(4) and L4(4))+(L1(4) and L3(4) and L4(4))+(L2(4) and L3(4) and L4(4));
RB3(5)<= (L1(5) and L2(5) and L3(5))+(L1(5) and L2(5) and L4(5))+(L1(5) and L3(5) and L4(5))+(L2(5) and L3(5) and L4(5));
RB3(6)<= (L1(6) and L2(6) and L3(6))+(L1(6) and L2(6) and L4(6))+(L1(6) and L3(6) and L4(6))+(L2(6) and L3(6) and L4(6));
RB3(7)<= (L1(7) and L2(7) and L3(7))+(L1(7) and L2(7) and L4(7))+(L1(7) and L3(7) and L4(7))+(L2(7) and L3(7) and L4(7));
when "10011111" =>
RB4(0)<= (L1(0) and L2(0) and L3(0))+(L1(0) and L2(0) and L4(0))+(L1(0) and L3(0) and L4(0))+(L2(0) and L3(0) and L4(0));
RB4(1)<= (L1(1) and L2(1) and L3(1))+(L1(1) and L2(1) and L4(1))+(L1(1) and L3(1) and L4(1))+(L2(1) and L3(1) and L4(1));
RB4(2)<= (L1(2) and L2(2) and L3(2))+(L1(2) and L2(2) and L4(2))+(L1(2) and L3(2) and L4(2))+(L2(2) and L3(2) and L4(2));
RB4(3)<= (L1(3) and L2(3) and L3(3))+(L1(3) and L2(3) and L4(3))+(L1(3) and L3(3) and L4(3))+(L2(3) and L3(3) and L4(3));
RB4(4)<= (L1(4) and L2(4) and L3(4))+(L1(4) and L2(4) and L4(4))+(L1(4) and L3(4) and L4(4))+(L2(4) and L3(4) and L4(4));
RB4(5)<= (L1(5) and L2(5) and L3(5))+(L1(5) and L2(5) and L4(5))+(L1(5) and L3(5) and L4(5))+(L2(5) and L3(5) and L4(5));
RB4(6)<= (L1(6) and L2(6) and L3(6))+(L1(6) and L2(6) and L4(6))+(L1(6) and L3(6) and L4(6))+(L2(6) and L3(6) and L4(6));
RB4(7)<= (L1(7) and L2(7) and L3(7))+(L1(7) and L2(7) and L4(7))+(L1(7) and L3(7) and L4(7))+(L2(7) and L3(7) and L4(7));
------------------------------
------------------------------
---------------------
--#(a,b,c,d) = (a*b*c)+(a*b*d)+(a*c*d)+(b*c*
end case;
-------check Z -----------------
if (RB1(0 to 7)="00000000") then
Z<='1';
end if;
if (RB2(0 to 7)="00000000") then
Z<='1';
end if;
if (RB3(0 to 7)="00000000") then
Z<='1';
end if;
if (RB4(0 to 7)="00000000") then
Z<='1';
end if;
------------------------------
end process logical_device;
END behavior;
Временные диаграммы работы устройства
Представленный тестовый пример разработан в среде Or CAD 9.1
Тест микрокоманды 1: Вход L5 <= “00IIJJFF”. Выход RBj <= RAi(F)RAj
Зададим L5 <= “00001101”.
Тогда RB4 <= RA1 and RA4.
В результате проделанной работы было синтезировали IP-ядро коммутационного микропроцессора. Процесс разработки был разбит на несколько этапов: создание графа переходов, характеризующего состояние системы микропроцессора, создание функциональных блок схем, разработка VHDL модели блоков устройства, отладка, оптимизация и компиляция VHDL модели. Для отладки и компиляции разрабатываемого устройства использовались пакеты программного обеспечения «Or CAD Release 9.1». Были получены временные диаграммы работы IP-ядра БИС КМП. В дальнейшем необходимо выполнить верификацию VHDL-модели в программном комплексе MAX+plus II 10.2 фирмы ALTERA и валидацию на плате FLEX 8000.
Информация о работе Разработка IP - ядра коммутационного микропроцессора